The present invention relates to an electronic device such as a semiconductor device and a printed wiring board, and a method of making the same. More particularly, the present invention relates to a technology for forming a multilayer wiring structure including a via connection.
In a process of producing a semiconductor device, wiring board, or the like, a multilayer interconnection is formed as follows. First, a photosensitive resin layer acting as an interlayer insulating layer is formed on a substrate with a circuit formed thereon, and then it is exposed to light and developed to form a via hole therein. Next, a copper layer is plated on the developed layer and a photoresist layer is then deposited on the copper layer. The photoresist layer is exposed to light and developed in the same manner as the above for patterning. In accordance with the patterned photoresist layer, the copper layer is etched and patterned to form a circuit and a via hole (or several such holes). Thus, a two-layered circuit structure is formed.
Where a multilayer circuit is formed, the aforementioned process has to be repeatedly conducted. A repeat of such a complicated process for each circuit layer results in lower productivity and higher production costs.
If there is a relatively big difference between the coefficients of thermal expansion of the substrate and a component which is to be mounted on the substrate, connection failure may result when both are subjected to elevated temperatures, thus lowering the reliability of the device. One possible approach to overcoming this problem is to provide an underfill resin in the small space between substrate and component. However, as technology progresses (and especially as increased wiring densities in smaller areas are demanded), the space between substrate and component is getting narrower and narrower, which makes it relatively difficult to adequately provide sufficient underfill, resulting in a possible filling failure. For this reason, it is desired to provide a reliable connection without filling an underfill resin.
In a conventional method of producing a built-up printed wiring board, there may be a case where a metallized circuit layer is formed on an insulating layer having a via hole, and another insulating layer having a via hole is then formed over the circuit layer. In this case, if the via holes in both insulating layers overlap in position and the via hole of the lower layer is not completely filled with metal, insulating resin of the upper insulating layer may flow into the unfilled space in the lower via hole. As a result, a recessed part is formed in the surface of the upper layer and defocusing occurs during the exposing step, so that the precise formation of a via hole with a desired diameter becomes relatively difficult. If the via hole of the lower layer is completely filled with metal such as copper, the above problem does not occur. However, in practice, it is often difficult to completely fill the lower via hole with metal.
It is believed, therefore, that an electronic device (e.g., printed wiring board) that can be made in an efficient manner while overing the aforementioned advantages of earlier methods and devices made by same would constitute a significant advancement in the art.
An object of the present invention is to provide an improved method for forming a multilayer wiring structure including a via connection on the structure""s substrate.
Another object of the present invention is to provide such a method which will result in a structure having more reliable connections between substrate and electronic device mounted on the substrate, by focusing on the coefficients of thermal expansion of various insulating layers laminated to the substrate.
According to one aspect of the invention, there is provided a method comprising the steps of providing a substrate, forming a circuit on the substrate, forming a non-photosensitive resin layer on the substrate, the non-photosensitive resin layer substantially covering the circuit, forming a photosensitive resin layer on the non-photosensitive resin layer, forming a patterned opening in the photosensitive resin layer relative to the circuit, forming a hole in the non-photosensitive resin layer to expose the circuit, and forming an electrically conductive layer on the non-photosensitive resin layer and the hole, the electrically conductive layer electrically coupled to the circuit.
According to a still further aspect of the invention, there is provided an electronic device comprising a substrate, a circuit positioned on the substrate, a first insulating layer positioned on the substrate substantially over the circuit and having a hole therein oriented directly above the circuit and contiguous thereto, a second insulating layer, positioned on the first insulating layer and including a patterned opening directly over the hole, formed of a material different from the first insulating layer, and formed on the first insulating layer in such a manner that the small hole is positioned in the larger hole, and an electrically conductive layer positioned on the non-photosensitive layer and substantially filling the hole, the electrically conductive layer being electrically coupled to the circuit.